#include "stm32f4xx.h"
#include "stm32f4xx_rcc.c"
#include "stm32f4xx_gpio.c"
#include "stm32f4xx_usart.c"
#include "stm32f4xx_dma.c"
#include "stm32f4xx_tim.c"
#include "stm32f4xx_adc.c"

#include "dd.h"

#define MAXRAW 4096

short unsigned volatile ADCraw[MAXRAW * 2 + 8];

// initialize port LEDS: pins 12, 13, 14, 15, port D as outputs
void GPIOD_LEDS (void)   {
GPIO_InitTypeDef  GPIO_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_OUT;
  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
  GPIO_Init(GPIOD, &GPIO_InitStructure); 
}

//USART3 initialization, GPIOD 8:9, TX&RX, IRQ on RX   
void USART3_init(int BaudRate)   {
USART_InitTypeDef       USART_InitStructure;  
GPIO_InitTypeDef        GPIO_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_8 | GPIO_Pin_9; 
  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;   
  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
  GPIO_Init(GPIOD, &GPIO_InitStructure); 
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_USART3);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_USART3);
  
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);  
  USART_DeInit(USART3);
  USART_InitStructure.USART_BaudRate            = BaudRate;  
  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
  USART_InitStructure.USART_Mode                = USART_Mode_Rx | USART_Mode_Tx;
  USART_InitStructure.USART_Parity              = USART_Parity_No;
  USART_InitStructure.USART_StopBits            = USART_StopBits_1;
  USART_InitStructure.USART_WordLength          = USART_WordLength_8b;
  USART_Init(USART3, &USART_InitStructure);

  USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); // enable IRQ on RX, disable on TX
  USART_Cmd(USART3, ENABLE);
  NVIC_EnableIRQ(USART3_IRQn);   // Enable IRQ for USART3 in NVIC
}

// ADC init function
void ADCinit_T3_TRGO_DMA (void)      {
ADC_InitTypeDef         ADC_InitStructure;
GPIO_InitTypeDef        GPIO_InitStructure;
ADC_CommonInitTypeDef   ADC_CommonInitStructure;
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1  | RCC_APB2Periph_ADC2,  ENABLE);
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB, ENABLE);
  
  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_1 | GPIO_Pin_2;
  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AN;
  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
  GPIO_Init(GPIOA, &GPIO_InitStructure); 
  
  ADC_CommonInitStructure.ADC_DMAAccessMode    = ADC_DMAAccessMode_2;
  ADC_CommonInitStructure.ADC_Mode             = ADC_DualMode_RegSimult;
  ADC_CommonInitStructure.ADC_Prescaler        = ADC_Prescaler_Div2;
  ADC_CommonInit(&ADC_CommonInitStructure);
    
  ADC_InitStructure.ADC_Resolution             = ADC_Resolution_12b;
  ADC_InitStructure.ADC_ScanConvMode           = DISABLE;
  ADC_InitStructure.ADC_ContinuousConvMode     = DISABLE;
  ADC_InitStructure.ADC_ExternalTrigConvEdge   = ADC_ExternalTrigConvEdge_Rising;
  ADC_InitStructure.ADC_ExternalTrigConv       = ADC_ExternalTrigConv_T3_TRGO;
  ADC_InitStructure.ADC_DataAlign              = ADC_DataAlign_Right;
  ADC_InitStructure.ADC_NbrOfConversion        = 1;
  ADC_Init(ADC1, &ADC_InitStructure);
  ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 1, ADC_SampleTime_3Cycles);

  ADC_Init(ADC2, &ADC_InitStructure);
  ADC_RegularChannelConfig(ADC2, ADC_Channel_2, 1, ADC_SampleTime_3Cycles);

  ADC_Cmd(ADC1, ENABLE);
  ADC_Cmd(ADC2, ENABLE);

}

// Timer 3 init function - time base
void TIM3init_ADCtrigger (int interval)  {
TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3,  ENABLE);
  TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
  TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
  TIM_TimeBaseInitStructure.TIM_Period = interval;
  TIM_TimeBaseInitStructure.TIM_Prescaler = 0;
  TIM_TimeBaseInitStructure.TIM_RepetitionCounter = 0;
  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseInitStructure);
  
  TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update); // SC (TRGO) on TIM3 update

  //TIM_Cmd(TIM3, ENABLE);
}   

//DMA1 initialization, TX requests next character to send
void DMA1forUSART3_init(void) {
DMA_InitTypeDef         DMA_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
  DMA_DeInit(DMA1_Stream3);                                       /* Reset DMA Stream registers (for debug purpose) */
  /* Configure DMA Stream */
  DMA_InitStructure.DMA_Channel                 = DMA_Channel_4;  
  DMA_InitStructure.DMA_PeripheralBaseAddr      = (uint32_t)(&USART3->DR);
  DMA_InitStructure.DMA_Memory0BaseAddr         = (uint32_t)(&ADCraw[0]);
  DMA_InitStructure.DMA_DIR                     = DMA_DIR_MemoryToPeripheral;
  DMA_InitStructure.DMA_BufferSize              = (uint32_t)8;
  DMA_InitStructure.DMA_PeripheralInc           = DMA_PeripheralInc_Disable;
  DMA_InitStructure.DMA_MemoryInc               = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize      = DMA_PeripheralDataSize_Byte;
  DMA_InitStructure.DMA_MemoryDataSize          = DMA_MemoryDataSize_Byte;
  DMA_InitStructure.DMA_Mode                    = DMA_Mode_Normal;
  DMA_InitStructure.DMA_Priority                = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode                = DMA_FIFOMode_Disable;         
  DMA_InitStructure.DMA_FIFOThreshold           = DMA_FIFOThreshold_Full;
  DMA_InitStructure.DMA_MemoryBurst             = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst         = DMA_PeripheralBurst_Single;
  DMA_Init(DMA1_Stream3, &DMA_InitStructure);
}

//DMA2 configuration, ADC1
void DMA2forADC1_init(void) {
DMA_InitTypeDef         DMA_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
  DMA_DeInit(DMA2_Stream3);                                       /* Reset DMA Stream registers (for debug purpose) */
  /* Configure DMA Stream */
  DMA_InitStructure.DMA_Channel                 = DMA_Channel_0;  
  DMA_InitStructure.DMA_PeripheralBaseAddr      = (uint32_t)(&ADC1->DR);
  DMA_InitStructure.DMA_Memory0BaseAddr         = (uint32_t)(&ADCraw[4]);
  DMA_InitStructure.DMA_DIR                     = DMA_DIR_PeripheralToMemory;
  DMA_InitStructure.DMA_BufferSize              = (uint32_t)MAXRAW;
  DMA_InitStructure.DMA_PeripheralInc           = DMA_PeripheralInc_Disable;
  DMA_InitStructure.DMA_MemoryInc               = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize      = DMA_PeripheralDataSize_HalfWord;
  DMA_InitStructure.DMA_MemoryDataSize          = DMA_MemoryDataSize_HalfWord;
  DMA_InitStructure.DMA_Mode                    = DMA_Mode_Normal;
  DMA_InitStructure.DMA_Priority                = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode                = DMA_FIFOMode_Disable;         
  DMA_InitStructure.DMA_FIFOThreshold           = DMA_FIFOThreshold_Full;
  DMA_InitStructure.DMA_MemoryBurst             = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst         = DMA_PeripheralBurst_Single;
  DMA_Init(DMA2_Stream0, &DMA_InitStructure);
  
  DMA_ITConfig(DMA2_Stream0, DMA_IT_TC, ENABLE);        // interrupt at the end of DMA transfer
  NVIC_EnableIRQ(DMA2_Stream0_IRQn);   // Enable IRQ for USART3 in NVIC

}

//DMA2 configuration, ADC2
void DMA2forADC2_init(void) {
DMA_InitTypeDef         DMA_InitStructure;
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
  DMA_DeInit(DMA2_Stream3);                                       /* Reset DMA Stream registers (for debug purpose) */
  /* Configure DMA Stream */
  DMA_InitStructure.DMA_Channel                 = DMA_Channel_1;  
  DMA_InitStructure.DMA_PeripheralBaseAddr      = (uint32_t)(&ADC2->DR);
  DMA_InitStructure.DMA_Memory0BaseAddr         = (uint32_t)(&ADCraw[MAXRAW+4]);
  DMA_InitStructure.DMA_DIR                     = DMA_DIR_PeripheralToMemory;
  DMA_InitStructure.DMA_BufferSize              = (uint32_t)MAXRAW;
  DMA_InitStructure.DMA_PeripheralInc           = DMA_PeripheralInc_Disable;
  DMA_InitStructure.DMA_MemoryInc               = DMA_MemoryInc_Enable;
  DMA_InitStructure.DMA_PeripheralDataSize      = DMA_PeripheralDataSize_HalfWord;
  DMA_InitStructure.DMA_MemoryDataSize          = DMA_MemoryDataSize_HalfWord;
  DMA_InitStructure.DMA_Mode                    = DMA_Mode_Normal;
  DMA_InitStructure.DMA_Priority                = DMA_Priority_High;
  DMA_InitStructure.DMA_FIFOMode                = DMA_FIFOMode_Disable;         
  DMA_InitStructure.DMA_FIFOThreshold           = DMA_FIFOThreshold_Full;
  DMA_InitStructure.DMA_MemoryBurst             = DMA_MemoryBurst_Single;
  DMA_InitStructure.DMA_PeripheralBurst         = DMA_PeripheralBurst_Single;
  DMA_Init(DMA2_Stream2, &DMA_InitStructure);
  
  DMA_ITConfig(DMA2_Stream2, DMA_IT_TC, ENABLE);        // interrupt at the end of DMA transfer
  NVIC_EnableIRQ(DMA2_Stream2_IRQn);   // Enable IRQ for USART3 in NVIC
}

void main(void) {              
  
  GPIOD_LEDS();
  USART3_init(921600);
  DMA1forUSART3_init();
  ADCinit_T3_TRGO_DMA();
  DMA2forADC1_init();
  DMA2forADC2_init();
  TIM3init_ADCtrigger(83);              // 1us intervals!

  ADCraw[0] = 0xffff;	
  ADCraw[1] = 0xffff;	
  ADCraw[2] = 0x0000;	
  ADCraw[3] = 0x0100;

  while (1) {
      //USART_ClearFlag(USART3, USART_FLAG_TC);           
      //USART_DMACmd(USART3, USART_DMAReq_Tx, ENABLE);    
      //DMA_ClearFlag(DMA1_Stream3, DMA_FLAG_TCIF3 | DMA_FLAG_HTIF3);            
      //DMA_Cmd(DMA1_Stream3, ENABLE);            // note: USART3->SR.TXE requests DMA 
 };
}

// IRQ function
// caution: placing breakpoints in IRQ corrupts the execution!  
// this happends due to the reading of the DR by the IAR and changes IRQ flags!
// I wasted sevaral hours to figure this out; do not step into the same trap.
void USART3_IRQHandler(void)     {  
  // RX IRQ part
  if (USART3->SR & USART_SR_RXNE) {   // if RXNE flag in SR is on then
    int RXch = USART3->DR;            // save received character & clear flag
    if (RXch == 'a') LED_BL_ON;       // to show we are alive
    if (RXch == 'b') LED_BL_OFF;      // to show we are alive
    if (RXch == 's') {                // actual start of DMA supported sampling
      	ADC1->CR2 &= ~ADC_CR2_DMA;	  ADC1->CR2 |=  ADC_CR2_DMA;
	ADC2->CR2 &= ~ADC_CR2_DMA;	  ADC2->CR2 |=  ADC_CR2_DMA;
        DMA_Cmd(DMA2_Stream0, ENABLE);
        DMA_Cmd(DMA2_Stream2, ENABLE);
	TIM_Cmd(TIM3, ENABLE);
	GPIOD->BSRRL = 0x8000;
    };       
  };
}

void DMA2_Stream0_IRQHandler(void)
{
  GPIOE->BSRRL = 0x0200;
  TIM_Cmd(TIM3, DISABLE);
  //LL_ADC_Disable(ADC1);
  DMA_Cmd(DMA2_Stream0, DISABLE);
  DMA_ClearFlag(DMA2_Stream0, DMA_FLAG_TCIF0 | DMA_FLAG_TEIF0);

  GPIOE->BSRRH = 0x0200;
}

void DMA2_Stream2_IRQHandler(void)
{
  GPIOE->BSRRL = 0x0800;
  TIM_Cmd(TIM3, DISABLE);
  //LL_ADC_Disable(ADC2);
  DMA_Cmd(DMA2_Stream2, DISABLE);
  DMA_ClearFlag(DMA2_Stream2, DMA_FLAG_TCIF2 | DMA_FLAG_TEIF2);

  GPIOD->BSRRH = 0x8000;
  TIM3->CNT = 0;

  DMA_SetCurrDataCounter(DMA1_Stream3, MAXRAW * 4 + 8);
  USART_DMACmd(USART3, USART_DMAReq_Tx, ENABLE);    
  DMA_ClearFlag(DMA1_Stream3, DMA_FLAG_TCIF3 | DMA_FLAG_HTIF3 | DMA_FLAG_FEIF3);            
  DMA_Cmd(DMA1_Stream3, ENABLE);            // note: USART3->SR.TXE requests DMA 

  GPIOE->BSRRH = 0x0800;
}