#include "stm32f4xx.h"

  /*
  DAC->CR       = 0x00010001 // Control Register
  DAC->SWTRIGR  = // SoftWare TRIGger Register
  DAC->DHR12R1  = // Data Holding Register, 12bit, Right aligned, ch1
  DAC->DHR12L1  = // Data Holding Register, 12bit, Left aligned, ch1
  DAC->DHR8R1   = // Data Holding Register,  8bit, Right aligned, ch1
  DAC->DHR12R2  = // Data Holding Register, 12bit, Right aligned, ch2
  DAC->DHR12L2  = // Data Holding Register, 12bit, Left aligned, ch2
  DAC->DHR8R2   = // Data Holding Register,  8bit, Right aligned, ch2
  DAC->DHR12RD  = // Data Holding Register, 12bit, Right aligned, Dual
  DAC->DHR12LD  = // Data Holding Register, 12bit, Left aligned, Dual
  DAC->DHR8RD   = // Data Holding Register,  8bit, Right aligned, Dual
  DAC->DOR1     = // Data Output Register, ch1, read only
  DAC->DOR2     = // Data Output Register, ch2, read only
  DAC->SR       = // Status Register
  
  outputs are at PA4 & PA5 -> pins must be enabled for analog!
                              GPIOA->MODER   |= 0x00000f00;         
  */


int main ()  {
unsigned int j;
  
  RCC->APB1ENR |= 0x20000000;           // Enable clock for DAC

  DAC->CR |= 0x00010001;                // DAC control reg, both channels ON
  GPIOA->MODER   |= 0x00000f00;         // MODE Register PortA, PA4 & PA5 are analog!
  
  while (1) {
    DAC->DHR12R1 = j & 0xfff;           // up ramp
    DAC->DHR12R2 = 0xfff - (j & 0xfff); // down ramp
    j = (j + 1) & 0x0fff;
  };

};